Senior Presilicon Dfx Design And Validation Engineer

Senior Presilicon Dfx Design And Validation Engineer
Empresa:

(Confidencial)


Lugar:

Cundinamarca


Área:

Otros

Senior Presilicon Dfx Design And Validation Engineer

Detalles de la oferta

Job Description

This position will work within a soft IP team from CIG which develops Type-C sub-system RTL and associated collaterals for Intel latest SOC products. The role will take part in definition, design and verification of DFx features required for Type-C sub-system. Responsibilities include (but not limited to):
- Participation in definition of DFx solutions for future test/debug/validation needs.
- RTL design of DFx units and global debug features within the sub-system.
- RTL verification of DFx features at various hierarchy levels.

Qualifications
The applicant should have Bachelor degree in (Electrical & Electronics or Computer or equivalent) Engineering or higher, and at least about 10 years of experience in RTL design and verification.
- Familiarity or experience in RTL design with Verilog and/or VHDL is required.
- Familiarity or experience with RTL verification and timing analysis/closure is required.
- Knowledge of high speed serial system interfaces (such as PCI Express or USB) is a strong plus.
- Familiarity with Perl, C++ and shell scripts is a plus.
- Strong skills in communication, driving initiative, promoting innovation and collaboration.
- Highly motivated to learn and adapt to fast-evolving technologies and environments.

Inside this Business Group

The Infrastructure and Platform Solutions Group (IPSG) builds the silicon and platform infrastructure for Intel's silicon design teams. IPSG is comprised of a reusable pool of infrastructure IP blocks, design enabling services such as tools and automation, and a best-in-class post silicon ecosystem that ramps quickly to high volume manufacturing and validation. Our primary mission is to protect Intel's brand by providing the infrastructure necessary to enable all of Intel's products to hit the market on a dependable and predictable cadence.

Malaysia, Kulim
MYExperienced HireJR0127895Penang


Fuente: Learn4Good


Área:

Requisitos


Conocimientos:

  • C++

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